The present invention relates to a microprocessor for performing an arithmetic operation on floating-point data and, more particularly, to a floating-point processor (called hereinafter "FPP") including an exception detector for detecting the occurrence of "Overflow" and "Underflow" exceptions in arithmetic resultant data.
As well known in the art, floating-data is represented by an exponent part and a mantissa part. For example, the exponent part consists of 16 bits and the mantissa part consists of 64 bits, as shown in FIG. 5A. The exponent part data is represented by 2's complement form and thus the most significant (or 15-th) bit (MSB) thereof indicates a sign of the exponent part data. The secondary more significant (or 14-th) bit of the exponent part data is used as an expanded bit for indicating an overflow condition of the actual exponent number represented by the remaining fourteen bits. A sign bit is further provided to indicate a sign of the floating-point data. Moreover, the floating-point data is treated in a normalized form. The normalized form indicates that the most significant (or 63-th) bit (MSB) of the mantissa part is "1", as also shown in FIG. 5A. The point of the mantissa part exists between the MSB and the secondary more significant (or 62-th) bit thereof.
In this data format, as shown in FIG. 5B, the normalized floating-point data is represented as a valid number if it is within a range from the data representing a valid floating-point maximum number, in which all the bits except the most significant two bits and the LSB of the exponent part and all the bits of the mantissa part are "1", to the data representing a valid floating-point minimum number, in which only the LSB of the exponent part and only the LSB of the mantissa part are "1". As also shown in FIG. 5B, the data in which the exponent part thereof is greater than the valid maximum number of the exponent part, i.e. all the bits except the most significant two bits are "1" or the expanded bit is "1", is defined as a mark representing infinity or uncertainty. The data in which all the bits of the exponent part are "0" is treated as a denormal number for interpolating between zero and the valid floating-point minimum number (the exponent part being 1 and only the MSB of the mantissa part being "1"). The data in which the MSB of the exponent part is "1" is defined as a default number.
When an arithmetic operation is performed on data according to the above data format, the resultant data often exceeds the range represented as the normalized valid number. The data having the exponent part data which is larger than the valid maximum number is called "Overflow" data, and the data having the exponent part data which is smaller than the valid minimum number is called "Underflow" data. As also well known in the art, the occurrence of Overflow and Underflow data is detected as an exception. Therefore, a detecting operation has to be performed for detecting whether or not Overflow or Underflow occurs in the arithmetic resultant data. For this purpose, the exponent part of the resultant data is detected. That is, when all the bits except the two most significant bits of the exponent part of the resultant data are "1", the Overflow exception is detected. When the exponent part of the resultant data is equal to or smaller than zero, the Underflow exception is detected.
However, the data of the exponent part may be changed by a rounding operation which is performed on the resultant data. More specifically, in the arithmetic operation of the floating-point data, the mantissa part of the resultant data often exceeds a predetermined data length (64 bits in the data format shown in FIG. 5). For example, in the case of the multiplication of the floating-point data, the mantissa part of the multiplication resultant data may have a data length twice longer than the predetermined data length. Therefore, an operation for adjusting the data length of the resultant data with the predetermined data length is required to complete the processing. This operation is called "rounding operation". Four rounding modes for the rounding operation, i.e. "rounding toward +.infin.", "rounding toward -.infin.", "rounding toward zero" and "rounding to nearest", are known. However, the rounding operation includes only two cases. The first case is to raise one unit to the place of the LSB of the mantissa part and the second case is to truncate the value underflowing LSB thereof. That is, the rounding operation is summarized as modifying the arithmetic resultant data by adding "1" to the LSB of the mantissa part or by truncating the underflowing value, depending upon the rounding modes and the resultant data. In order to determine the rounding operation by raising or truncating, the mantissa part of the resultant data is added with a round bit and a sticky bit, as shown in FIG. 5C. The round bit represents the data of the most significant bit of the underflowing value and the sticky bit represents the logic-ORed data of the underflowing value except the MSB thereof. In accordance with contents of the sign bit, the LSB of the mantissa part, the round bit and the sticky bit and the designated rounding mode, the rounding operation by raising or truncating is determined. When rounding by raising, the mantissa part of the resultant data is added with "1". As a result, an overflow bit may be produced from the mantissa part, as shown in FIG. 5C. In this case, the exponent part of the resultant data is added with "1" and the mantissa part thereof is shifted by one in the direction of the LSB in order to normalize the resultant data subjected to the rounding operation. Thus, the exponent part data of the resultant data may be changed by the rounding operation.
For example, assuming that all the bits except the most significant two bits and the LSB of the exponent part of the normalized resultant data are "1" and all the bits of the mantissa part thereof are "1" as shown in FIG. 6A, the exponent part data is a valid maximum number and thus no Overflow exception occurs in this data. However, if the rounding operation by raising is designated and performed, an overflow bit is produced from the mantissa part, so that the normalized data exceeds the valid maximum number. This means the occurrence of the Overflow exception. As another example shown in FIG. 6B, when all the bits of the exponent part of the resultant data are "0" and all the bits of the mantissa part thereof are "1", this resultant data is the denormal number and thus the Underflow exception occurs therein. However, if the rounding operation by raising is designated and performed, an overflow bit is produced from the mantissa part, so that the normalized data is free from the Underflow exception.
Thus, since the exponent part data may be changed by the rounding operation, the exception detector according to the prior art performs the exception detecting operation on the normalized exponent part data. In order to obtain the normalized exponent part data, such a sequential operation is required that the mantissa part data is first added with "1" if the rounding operation by raising is designated and thereafter the exponent part data is added with "1" if the overflow bit is produced from the mantissa part. For this reason, the exception detecting operation is not preformed at a high speed.